Test MP+clflush+mfence+UC+WB

X86_64 MP+clflush+mfence+UC+WB
"ClFlushdWW Rfe MFencedRR Fre"
MT=x:UC y:WB
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=ClFlushdWW Rfe MFencedRR Fre
Align=
{
}
 P0          | P1            ;
 movl $1,(x) | movl (y),%eax ;
 clflush (x) | mfence        ;
 movl $1,(y) | movl (x),%ebx ;
exists (1:rax=1 /\ 1:rbx=0)