Test SB+clflushopts+WC+WC

X86_64 SB+clflushopts+WC+WC
"ClFlushOptdWR Fre ClFlushOptdWR Fre"
MT=x:WC y:WC
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=ClFlushOptdWR Fre ClFlushOptdWR Fre
Align=
{
}
 P0             | P1             ;
 movl $1,(x)    | movl $1,(y)    ;
 clflushopt (x) | clflushopt (y) ;
 movl (y),%eax  | movl (x),%eax  ;
exists (0:rax=0 /\ 1:rax=0)