Test SB+clflushnexts+UC+UC

X86_64 SB+clflushnexts+UC+UC
"ClFlushNextdWR Fre ClFlushNextdWR Fre"
MT=x:UC y:UC
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=ClFlushNextdWR Fre ClFlushNextdWR Fre
Align=
{
}
 P0            | P1            ;
 movl $1,(x)   | movl $1,(y)   ;
 clflush (y)   | clflush (x)   ;
 movl (y),%eax | movl (x),%eax ;
exists (0:rax=0 /\ 1:rax=0)