Test Z6.0+WB+UC+WB

X86_64 Z6.0+WB+UC+WB
"PodWW Rfe PodRW Coe PodWR Fre"
MT=x:WB,y:UC,z:WB
Cycle=Rfe PodRW Coe PodWR Fre PodWW
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Co Fr
Orig=PodWW Rfe PodRW Coe PodWR Fre
Align=
{
}
 P0          | P1            | P2            ;
 movl $1,(x) | movl (y),%eax | movl $2,(z)   ;
 movl $1,(y) | movl $1,(z)   | movl (x),%eax ;
exists (z=2 /\ 1:rax=1 /\ 2:rax=0)