Test ISA2+WC+WC+UC

X86_64 ISA2+WC+WC+UC
"PodWW Rfe PodRW Rfe PodRR Fre"
MT=x:WC,y:WC,z:UC
Cycle=Rfe PodRW Rfe PodRR Fre PodWW
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Rf Fr
Orig=PodWW Rfe PodRW Rfe PodRR Fre
Align=
{
}
 P0          | P1            | P2            ;
 movl $1,(x) | movl (y),%eax | movl (z),%eax ;
 movl $1,(y) | movl $1,(z)   | movl (x),%ebx ;
exists (1:rax=1 /\ 2:rax=1 /\ 2:rbx=0)