Test LB+WC+WT+NT

X86_64 LB+WC+WT+NT
"PodRWNaNT RfeNTNa PodRWNaNT RfeNTNa"
MT=x:WC y:WT
Cycle=PodRWNaNT RfeNTNa PodRWNaNT RfeNTNa
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=PodRWNaNT RfeNTNa PodRWNaNT RfeNTNa
Align=
{
0:rbx=y;
1:rbx=x;
}
 P0                  | P1                  ;
 movl (x),%eax       | movl (y),%eax       ;
 movl $1,%ecx        | movl $1,%ecx        ;
 movntil %ecx,(%rbx) | movntil %ecx,(%rbx) ;
exists (x=1 /\ y=1 /\ 0:rax=1 /\ 1:rax=1)