(*
* The Armv8 Application Level Memory Model.
*
* This is a machine-readable, executable and formal artefact, which aims to be
* the latest stable version of the Armv8 memory model.
* If you have comments on the content of this file, please send an email to
* memory-model@arm.com
* For a textual version of the model, see section B2.3 of the Armv8 ARM:
* https://developer.arm.com/documentation/ddi0487/
*
* Authors:
* Will Deacon
* Jade Alglave
* Nikos Nikoleris
* Artem Khyzha
*
* Copyright (C) 2016-present, Arm Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of ARM nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*)
(*
* Include default definitions for sets that are undefined without
* -variant vmsa
*)
let PTE = if "vmsa" then PTE else emptyset
let PTEV = if "vmsa" then PTEV else emptyset
let PTEINV = if "vmsa" then PTEINV else emptyset
let inv-domain = if "vmsa" then inv-domain else 0
let AF = if "vmsa" then AF else emptyset
let DB = if "vmsa" then DB else emptyset
let MMU = if "vmsa" then MMU else emptyset
let Translation = if "vmsa" then Translation else emptyset
let AccessFlag = if "vmsa" then AccessFlag else emptyset
(*
* Include default definitions for sets that might be undefined without
* -variant ifetch
*)
let Instr = if "ifetch" then Instr else emptyset
let Within-CMODX-List = if "ifetch" then Restricted-CMODX else emptyset
(*
* Include the cos.cat file shipped with herd.
* This builds the co relation as a total order over writes to the same
* location and then consequently defines the fr relation using co and
* rf.
*)
let AFtoDB = same-instance & ((AF\DB) * (DB\AF))
let co0=co0 | AFtoDB
include "cos.cat"
(*
* A shorthand for cache maintenance effects used by -variant ifetch
*)
let IC = IC.IALLUIS | IC.IALLU | IC.IVAU
(*
* Include aarch64fences.cat to define barriers.
*)
include "aarch64fences.cat"
(*
* Include aarch64bbm.cat to define relations on Break-Before-Make semantics.
*)
include "aarch64bbm.cat"
(* Show relations in generated diagrams *)
include "aarch64show.cat"
(* Helper functions *)
procedure included(r1, r2) =
empty r1 \ r2
end
procedure equal(r1, r2) =
call included(r1, r2)
call included(r2, r1)
end
(* Intervening Effect *)
let intervening(S,r) = r; [S]; r
(* Properties of single-copy atomic accesses *)
let sca-class = [M & Exp]; sm; [M & Exp]
(* Renaming default herd names *)
let Imp = NExp
let SPONTANEOUS = SPURIOUS
let inv-scope = inv-domain
let TTD = PTE
let Tag = T
(* Flag any occurrence of writes to two different locations that might be on
* the same cache line. *)
flag ~empty ((W & Instr)*(W & Instr) \ loc)
as Assuming-no-two-modified-instructions-are-on-the-same-cache-line
(* Flag the runs of herd7 with unsupported combinations of variants *)
flag ~empty (if "vmsa" && "memtag" then _ else 0)
as combining-vmsa-and-memtag-is-not-supported
flag ~empty (if "vmsa" && "ifetch" then _ else 0)
as combining-vmsa-and-ifetch-is-not-supported
flag ~empty (if "memtag" && "ifetch" then _ else 0)
as combining-memtag-and-ifetch-is-not-supported
(* Flag the runs of herd7 with work-in-progress features *)
flag ~empty (if "sve" then _ else 0)
as Scalable-Vector-Extensions-is-work-in-progress
include "aarch64loc.cat"