Test W+RW

Executions for behaviour: "1:R0=1 ; x=1"

ARM W+RW
"Rfe PosRW Wse"
Cycle=Rfe PosRW Wse
Relax=
Safe=Rfe Wse PosRW
Prefetch=
Com=Rf Ws
Orig=Rfe PosRW Wse
{
%x0=x;
%x1=x;
}
 P0           | P1           ;
 MOV R0,#1    | LDR R0,[%x1] ;
 STR R0,[%x0] | MOV R1,#2    ;
              | STR R1,[%x1] ;
exists x=1 /\ 1:R0=1