Executions for behaviour: "1:R0=1 ; 1:R1=0"
ARM W+RR "Rfe PosRR Fre" Cycle=Rfe PosRR Fre Relax= Safe=Rfe Fre PosRR Prefetch= Com=Rf Fr Orig=Rfe PosRR Fre { %x0=x; %x1=x; } P0 | P1 ; MOV R0,#1 | LDR R0,[%x1] ; STR R0,[%x0] | LDR R1,[%x1] ; exists 1:R0=1 /\ 1:R1=0