Wed Dec 30 10:06:07 CET 2009 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for ./src/aclwsrr000.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC aclwsrr000 "DpdR Fre SyncdWW Wse Rfe LwSyncsRR" {0:r2=x; 0:r4=y; 1:r2=y; 2:r2=y; 2:r6=x;} P0 | P1 | P2 ; li r1,1 | li r1,2 | lwz r1,0(r2) ; stw r1,0(r2) | stw r1,0(r2) | lwsync ; sync | | lwz r3,0(r2) ; li r3,1 | | xor r4,r3,r3 ; stw r3,0(r4) | | lwzx r5,r4,r6 ; exists (y=2 /\ 2:r1=2 /\ 2:r3=2 /\ 2:r5=0) Generated assembler _litmus_P0_0_: li r10,1 _litmus_P0_1_: stw r10,0(r9) _litmus_P0_2_: sync _litmus_P0_3_: li r11,1 _litmus_P0_4_: stw r11,0(r2) _litmus_P1_0_: li r9,2 _litmus_P1_1_: stw r9,0(r2) _litmus_P2_0_: lwz r4,0(r9) _litmus_P2_1_: lwsync _litmus_P2_2_: lwz r5,0(r9) _litmus_P2_3_: xor r10,r5,r5 _litmus_P2_4_: lwzx r11,r10,r2 Test aclwsrr000 Allowed Histogram (16 states) 60 :>2:r1=1; 2:r3=2; 2:r5=1; y=2; 66 :>2:r1=0; 2:r3=1; 2:r5=1; y=2; 541 :>2:r1=2; 2:r3=1; 2:r5=1; y=1; 177 :>2:r1=0; 2:r3=2; 2:r5=0; y=1; 301 :>2:r1=0; 2:r3=2; 2:r5=1; y=2; 3998 :>2:r1=0; 2:r3=1; 2:r5=1; y=1; 25364 :>2:r1=0; 2:r3=0; 2:r5=0; y=2; 4912795:>2:r1=2; 2:r3=2; 2:r5=0; y=1; 1084244:>2:r1=2; 2:r3=2; 2:r5=1; y=2; 3524514:>2:r1=0; 2:r3=0; 2:r5=1; y=1; 2506563:>2:r1=0; 2:r3=0; 2:r5=1; y=2; 1319114:>2:r1=1; 2:r3=1; 2:r5=1; y=2; 10478709:>2:r1=2; 2:r3=2; 2:r5=1; y=1; 12658900:>2:r1=0; 2:r3=0; 2:r5=0; y=1; 3480654:>2:r1=1; 2:r3=1; 2:r5=1; y=1; 4000 :>2:r1=0; 2:r3=2; 2:r5=1; y=1; No Witnesses Positive: 0, Negative: 40000000 Condition exists (y=2 /\ 2:r1=2 /\ 2:r3=2 /\ 2:r5=0) is NOT validated Hash=0e168a11add8ac7b91db489d5c03a6a4 Cycle=DpdR Fre SyncdWW Wse Rfe LwSyncsRR Relax aclwsrr000 No ACLwSyncsRR Safe=Fre Wse SyncdWW DpdR Time aclwsrr000 72.07 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for ./src/aclwsrr001.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC aclwsrr001 "DpdR Fre SyncdWW Rfe LwSyncsRR Fre Rfe LwSyncsRR" {0:r2=x; 0:r4=y; 1:r2=y; 2:r2=y; 3:r2=y; 3:r6=x;} P0 | P1 | P2 | P3 ; li r1,1 | lwz r1,0(r2) | li r1,2 | lwz r1,0(r2) ; stw r1,0(r2) | lwsync | stw r1,0(r2) | lwsync ; sync | lwz r3,0(r2) | | lwz r3,0(r2) ; li r3,1 | | | xor r4,r3,r3 ; stw r3,0(r4) | | | lwzx r5,r4,r6 ; exists (y=2 /\ 1:r1=1 /\ 1:r3=1 /\ 3:r1=2 /\ 3:r3=2 /\ 3:r5=0) Generated assembler _litmus_P0_0_: li r11,1 _litmus_P0_1_: stw r11,0(r9) _litmus_P0_2_: sync _litmus_P0_3_: li r10,1 _litmus_P0_4_: stw r10,0(r2) _litmus_P1_0_: lwz r8,0(r2) _litmus_P1_1_: lwsync _litmus_P1_2_: lwz r9,0(r2) _litmus_P2_0_: li r9,2 _litmus_P2_1_: stw r9,0(r2) _litmus_P3_0_: lwz r4,0(r9) _litmus_P3_1_: lwsync _litmus_P3_2_: lwz r5,0(r9) _litmus_P3_3_: xor r10,r5,r5 _litmus_P3_4_: lwzx r11,r10,r2 Test aclwsrr001 Allowed Histogram (88 states) 2 :>1:r1=1; 1:r3=1; 3:r1=0; 3:r3=2; 3:r5=0; y=1; 1 :>1:r1=0; 1:r3=1; 3:r1=0; 3:r3=2; 3:r5=0; y=1; 10 :>1:r1=0; 1:r3=2; 3:r1=0; 3:r3=2; 3:r5=0; y=1; 5 :>1:r1=0; 1:r3=1; 3:r1=0; 3:r3=1; 3:r5=1; y=2; 5 :>1:r1=0; 1:r3=1; 3:r1=0; 3:r3=2; 3:r5=1; y=2; 6 :>1:r1=0; 1:r3=2; 3:r1=2; 3:r3=1; 3:r5=1; y=1; 9 :>1:r1=0; 1:r3=1; 3:r1=0; 3:r3=0; 3:r5=0; y=2; 3 :>1:r1=2; 1:r3=1; 3:r1=0; 3:r3=2; 3:r5=1; y=1; 2 :>1:r1=2; 1:r3=1; 3:r1=0; 3:r3=1; 3:r5=1; y=1; 37 :>1:r1=1; 1:r3=1; 3:r1=1; 3:r3=2; 3:r5=1; y=2; 2 :>1:r1=1; 1:r3=2; 3:r1=0; 3:r3=2; 3:r5=1; y=2; 87 :>1:r1=2; 1:r3=2; 3:r1=1; 3:r3=2; 3:r5=1; y=2; 41 :>1:r1=0; 1:r3=1; 3:r1=0; 3:r3=1; 3:r5=1; y=1; 31 :>1:r1=0; 1:r3=2; 3:r1=0; 3:r3=2; 3:r5=1; y=2; 15 :>1:r1=0; 1:r3=2; 3:r1=0; 3:r3=1; 3:r5=1; y=1; 911 :>1:r1=2; 1:r3=2; 3:r1=0; 3:r3=1; 3:r5=1; y=2; 94 :>1:r1=0; 1:r3=2; 3:r1=0; 3:r3=0; 3:r5=0; y=2; 145 :>1:r1=0; 1:r3=1; 3:r1=2; 3:r3=2; 3:r5=1; y=2; 19 :>1:r1=0; 1:r3=1; 3:r1=0; 3:r3=2; 3:r5=1; y=1; 611 :>1:r1=0; 1:r3=0; 3:r1=1; 3:r3=2; 3:r5=1; y=2; 40 :>1:r1=0; 1:r3=1; 3:r1=2; 3:r3=2; 3:r5=0; y=1; 19094 :>1:r1=0; 1:r3=1; 3:r1=0; 3:r3=0; 3:r5=0; y=1; 16491 :>1:r1=0; 1:r3=0; 3:r1=2; 3:r3=1; 3:r5=1; y=1; 125049:>1:r1=0; 1:r3=2; 3:r1=0; 3:r3=0; 3:r5=0; y=1; 206 :>1:r1=2; 1:r3=1; 3:r1=2; 3:r3=2; 3:r5=0; y=1; 34 :>1:r1=0; 1:r3=2; 3:r1=0; 3:r3=2; 3:r5=1; y=1; 1970 :>1:r1=1; 1:r3=1; 3:r1=0; 3:r3=2; 3:r5=1; y=1; 1412 :>1:r1=0; 1:r3=2; 3:r1=2; 3:r3=2; 3:r5=0; y=1; 3867 :>1:r1=1; 1:r3=1; 3:r1=2; 3:r3=2; 3:r5=0; y=1; 1617 :>1:r1=0; 1:r3=0; 3:r1=0; 3:r3=1; 3:r5=1; y=2; 662 :>1:r1=2; 1:r3=1; 3:r1=0; 3:r3=0; 3:r5=0; y=1; 21327 :>1:r1=2; 1:r3=2; 3:r1=0; 3:r3=2; 3:r5=1; y=2; 142 :>1:r1=2; 1:r3=1; 3:r1=0; 3:r3=0; 3:r5=1; y=1; 207 :>1:r1=1; 1:r3=2; 3:r1=1; 3:r3=1; 3:r5=1; y=2; 4465 :>1:r1=1; 1:r3=1; 3:r1=0; 3:r3=1; 3:r5=1; y=2; 7 :>1:r1=0; 1:r3=1; 3:r1=2; 3:r3=1; 3:r5=1; y=1; 7607 :>1:r1=2; 1:r3=2; 3:r1=0; 3:r3=1; 3:r5=1; y=1; 12390 :>1:r1=1; 1:r3=1; 3:r1=0; 3:r3=2; 3:r5=1; y=2; 123 :>1:r1=1; 1:r3=2; 3:r1=2; 3:r3=2; 3:r5=1; y=2; 641 :>1:r1=2; 1:r3=2; 3:r1=0; 3:r3=2; 3:r5=0; y=1; 1718 :>1:r1=2; 1:r3=1; 3:r1=2; 3:r3=2; 3:r5=1; y=1; 489 :>1:r1=1; 1:r3=1; 3:r1=0; 3:r3=0; 3:r5=0; y=2; 2089 :>1:r1=0; 1:r3=2; 3:r1=1; 3:r3=1; 3:r5=1; y=1; 1350 :>1:r1=1; 1:r3=1; 3:r1=2; 3:r3=1; 3:r5=1; y=1; 348 :>1:r1=2; 1:r3=2; 3:r1=0; 3:r3=0; 3:r5=0; y=2; 658 :>1:r1=0; 1:r3=1; 3:r1=1; 3:r3=1; 3:r5=1; y=2; 14813 :>1:r1=2; 1:r3=2; 3:r1=0; 3:r3=2; 3:r5=1; y=1; 23607 :>1:r1=0; 1:r3=0; 3:r1=0; 3:r3=2; 3:r5=0; y=1; 6006 :>1:r1=0; 1:r3=0; 3:r1=0; 3:r3=2; 3:r5=1; y=2; 1338 :>1:r1=0; 1:r3=2; 3:r1=1; 3:r3=1; 3:r5=1; y=2; 7357 :>1:r1=0; 1:r3=1; 3:r1=1; 3:r3=1; 3:r5=1; y=1; 4459 :>1:r1=2; 1:r3=1; 3:r1=1; 3:r3=1; 3:r5=1; y=1; 293 :>1:r1=1; 1:r3=2; 3:r1=0; 3:r3=0; 3:r5=1; y=2; 10227 :>1:r1=0; 1:r3=2; 3:r1=2; 3:r3=2; 3:r5=1; y=1; 19181 :>1:r1=1; 1:r3=1; 3:r1=0; 3:r3=1; 3:r5=1; y=1; 2522 :>1:r1=0; 1:r3=2; 3:r1=2; 3:r3=2; 3:r5=1; y=2; 5388 :>1:r1=0; 1:r3=1; 3:r1=2; 3:r3=2; 3:r5=1; y=1; 17629 :>1:r1=2; 1:r3=2; 3:r1=2; 3:r3=1; 3:r5=1; y=1; 5245 :>1:r1=0; 1:r3=1; 3:r1=0; 3:r3=0; 3:r5=1; y=1; 61665 :>1:r1=0; 1:r3=0; 3:r1=0; 3:r3=0; 3:r5=0; y=2; 62373 :>1:r1=1; 1:r3=1; 3:r1=2; 3:r3=2; 3:r5=1; y=2; 26580 :>1:r1=0; 1:r3=0; 3:r1=0; 3:r3=1; 3:r5=1; y=1; 7948 :>1:r1=0; 1:r3=2; 3:r1=0; 3:r3=0; 3:r5=1; y=1; 79375 :>1:r1=2; 1:r3=2; 3:r1=1; 3:r3=1; 3:r5=1; y=2; 152299:>1:r1=1; 1:r3=1; 3:r1=1; 3:r3=1; 3:r5=1; y=2; 142404:>1:r1=2; 1:r3=2; 3:r1=2; 3:r3=2; 3:r5=1; y=2; 1789869:>1:r1=1; 1:r3=1; 3:r1=1; 3:r3=1; 3:r5=1; y=1; 3576 :>1:r1=0; 1:r3=2; 3:r1=0; 3:r3=0; 3:r5=1; y=2; 106530:>1:r1=1; 1:r3=1; 3:r1=0; 3:r3=0; 3:r5=0; y=1; 793400:>1:r1=2; 1:r3=2; 3:r1=0; 3:r3=0; 3:r5=1; y=2; 851402:>1:r1=0; 1:r3=0; 3:r1=1; 3:r3=1; 3:r5=1; y=1; 846963:>1:r1=0; 1:r3=0; 3:r1=2; 3:r3=2; 3:r5=1; y=2; 974 :>1:r1=0; 1:r3=1; 3:r1=0; 3:r3=0; 3:r5=1; y=2; 1175755:>1:r1=2; 1:r3=2; 3:r1=1; 3:r3=1; 3:r5=1; y=1; 854366:>1:r1=1; 1:r3=1; 3:r1=0; 3:r3=0; 3:r5=1; y=2; 172788:>1:r1=0; 1:r3=0; 3:r1=0; 3:r3=2; 3:r5=1; y=1; 1026135:>1:r1=0; 1:r3=0; 3:r1=0; 3:r3=0; 3:r5=1; y=2; 517114:>1:r1=1; 1:r3=1; 3:r1=2; 3:r3=2; 3:r5=1; y=1; 4643577:>1:r1=2; 1:r3=2; 3:r1=0; 3:r3=0; 3:r5=0; y=1; 462158:>1:r1=1; 1:r3=1; 3:r1=0; 3:r3=0; 3:r5=1; y=1; 5038272:>1:r1=0; 1:r3=0; 3:r1=2; 3:r3=2; 3:r5=1; y=1; 374043:>1:r1=2; 1:r3=2; 3:r1=0; 3:r3=0; 3:r5=1; y=1; 1305027:>1:r1=0; 1:r3=0; 3:r1=2; 3:r3=2; 3:r5=0; y=1; 2075948:>1:r1=0; 1:r3=0; 3:r1=0; 3:r3=0; 3:r5=1; y=1; 6550653:>1:r1=0; 1:r3=0; 3:r1=0; 3:r3=0; 3:r5=0; y=1; 7032948:>1:r1=2; 1:r3=2; 3:r1=2; 3:r3=2; 3:r5=1; y=1; 929628:>1:r1=0; 1:r3=0; 3:r1=1; 3:r3=1; 3:r5=1; y=2; 2572126:>1:r1=2; 1:r3=2; 3:r1=2; 3:r3=2; 3:r5=0; y=1; No Witnesses Positive: 0, Negative: 40000000 Condition exists (y=2 /\ 1:r1=1 /\ 1:r3=1 /\ 3:r1=2 /\ 3:r3=2 /\ 3:r5=0) is NOT validated Hash=c675ca6562f64b0057e406348aad3876 Cycle=DpdR Fre SyncdWW Rfe LwSyncsRR Fre Rfe LwSyncsRR Relax aclwsrr001 No ACLwSyncsRR Safe=Fre SyncdWW DpdR Time aclwsrr001 201.13 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Results for ./src/aclwsrr002.litmus % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% PPC aclwsrr002 "DpdR Fre Rfe LwSyncsRR DpdR Fre Rfe LwSyncsRR" {0:r2=x; 0:r6=y; 1:r2=y; 2:r2=y; 2:r6=x; 3:r2=x;} P0 | P1 | P2 | P3 ; lwz r1,0(r2) | li r1,1 | lwz r1,0(r2) | li r1,1 ; lwsync | stw r1,0(r2) | lwsync | stw r1,0(r2) ; lwz r3,0(r2) | | lwz r3,0(r2) | ; xor r4,r3,r3 | | xor r4,r3,r3 | ; lwzx r5,r4,r6 | | lwzx r5,r4,r6 | ; exists (0:r1=1 /\ 0:r3=1 /\ 0:r5=0 /\ 2:r1=1 /\ 2:r3=1 /\ 2:r5=0) Generated assembler _litmus_P0_0_: lwz r4,0(r9) _litmus_P0_1_: lwsync _litmus_P0_2_: lwz r5,0(r9) _litmus_P0_3_: xor r10,r5,r5 _litmus_P0_4_: lwzx r11,r10,r2 _litmus_P1_0_: li r9,1 _litmus_P1_1_: stw r9,0(r2) _litmus_P2_0_: lwz r4,0(r9) _litmus_P2_1_: lwsync _litmus_P2_2_: lwz r5,0(r9) _litmus_P2_3_: xor r10,r5,r5 _litmus_P2_4_: lwzx r11,r10,r2 _litmus_P3_0_: li r9,1 _litmus_P3_1_: stw r9,0(r2) Test aclwsrr002 Allowed Histogram (31 states) 1 :>0:r1=0; 0:r3=1; 0:r5=0; 2:r1=0; 2:r3=1; 2:r5=1; 612 :>0:r1=0; 0:r3=1; 0:r5=0; 2:r1=0; 2:r3=0; 2:r5=0; 100 :>0:r1=1; 0:r3=1; 0:r5=1; 2:r1=0; 2:r3=1; 2:r5=0; 194 :>0:r1=0; 0:r3=0; 0:r5=0; 2:r1=0; 2:r3=1; 2:r5=0; 125 :>0:r1=0; 0:r3=1; 0:r5=0; 2:r1=1; 2:r3=1; 2:r5=1; 11045 :>0:r1=1; 0:r3=1; 0:r5=0; 2:r1=0; 2:r3=1; 2:r5=1; 143 :>0:r1=0; 0:r3=1; 0:r5=1; 2:r1=0; 2:r3=1; 2:r5=1; 143 :>0:r1=0; 0:r3=0; 0:r5=1; 2:r1=0; 2:r3=1; 2:r5=0; 349 :>0:r1=0; 0:r3=1; 0:r5=0; 2:r1=0; 2:r3=0; 2:r5=1; 169836:>0:r1=1; 0:r3=1; 0:r5=0; 2:r1=0; 2:r3=0; 2:r5=0; 9229 :>0:r1=0; 0:r3=1; 0:r5=1; 2:r1=0; 2:r3=0; 2:r5=1; 6435 :>0:r1=0; 0:r3=0; 0:r5=1; 2:r1=0; 2:r3=1; 2:r5=1; 90667 :>0:r1=0; 0:r3=0; 0:r5=0; 2:r1=1; 2:r3=1; 2:r5=0; 31951 :>0:r1=0; 0:r3=1; 0:r5=1; 2:r1=0; 2:r3=0; 2:r5=0; 5151 :>0:r1=0; 0:r3=1; 0:r5=1; 2:r1=1; 2:r3=1; 2:r5=0; 123633:>0:r1=0; 0:r3=1; 0:r5=1; 2:r1=1; 2:r3=1; 2:r5=1; 615202:>0:r1=1; 0:r3=1; 0:r5=0; 2:r1=0; 2:r3=0; 2:r5=1; 238022:>0:r1=1; 0:r3=1; 0:r5=0; 2:r1=1; 2:r3=1; 2:r5=1; 107147:>0:r1=1; 0:r3=1; 0:r5=1; 2:r1=0; 2:r3=1; 2:r5=1; 153038:>0:r1=0; 0:r3=0; 0:r5=1; 2:r1=0; 2:r3=0; 2:r5=1; 128772:>0:r1=1; 0:r3=1; 0:r5=1; 2:r1=1; 2:r3=1; 2:r5=0; 46691 :>0:r1=0; 0:r3=0; 0:r5=0; 2:r1=0; 2:r3=1; 2:r5=1; 2183743:>0:r1=0; 0:r3=0; 0:r5=1; 2:r1=1; 2:r3=1; 2:r5=1; 389066:>0:r1=0; 0:r3=0; 0:r5=1; 2:r1=1; 2:r3=1; 2:r5=0; 3908698:>0:r1=0; 0:r3=0; 0:r5=0; 2:r1=0; 2:r3=0; 2:r5=1; 4073504:>0:r1=0; 0:r3=0; 0:r5=1; 2:r1=0; 2:r3=0; 2:r5=0; 4515254:>0:r1=0; 0:r3=0; 0:r5=0; 2:r1=1; 2:r3=1; 2:r5=1; 15350885:>0:r1=1; 0:r3=1; 0:r5=1; 2:r1=1; 2:r3=1; 2:r5=1; 4053761:>0:r1=1; 0:r3=1; 0:r5=1; 2:r1=0; 2:r3=0; 2:r5=0; 1202552:>0:r1=0; 0:r3=0; 0:r5=0; 2:r1=0; 2:r3=0; 2:r5=0; 2584051:>0:r1=1; 0:r3=1; 0:r5=1; 2:r1=0; 2:r3=0; 2:r5=1; No Witnesses Positive: 0, Negative: 40000000 Condition exists (0:r1=1 /\ 0:r3=1 /\ 0:r5=0 /\ 2:r1=1 /\ 2:r3=1 /\ 2:r5=0) is NOT validated Hash=050ce9f57369bcd60ead287482f2d6b6 Cycle=DpdR Fre Rfe LwSyncsRR DpdR Fre Rfe LwSyncsRR Relax aclwsrr002 No ACLwSyncsRR Safe=Fre DpdR Time aclwsrr002 95.61 $Revision: 3163 $ Parameters #ifndef SIZE_OF_TEST #define SIZE_OF_TEST 1000000 #endif #ifndef NUMBER_OF_RUN #define NUMBER_OF_RUN 1 #endif #ifndef N_EXE #define N_EXE (4 < N ? 1 : 4 / N) #endif /* gcc options: -Wall -std=gnu99 */ /* barrier: user */ /* tread start/join: changing */ /* memory: indirect */ /* safer: true */ /* preload: true */ /* para: self */ /* changes: false */ /* speedcheck: false */ /* proc used: 4 */ GCCOPTS="-Wall -std=gnu99 " LITMUSOPTS=-r 40 Wed Dec 30 10:12:15 CET 2009