PPC bclwsrw024 "LwSyncsRR DpdR Fre SyncsWR DpdR LwSyncsRW Rfe" Cycle=LwSyncsRR DpdR Fre SyncsWR DpdR LwSyncsRW Rfe Relax=BCLwSyncsRW Safe=Fre SyncsWR LwSyncsRR DpdR { 0:r2=x; 0:r6=y; 1:r2=y; 1:r6=x; } P0 | P1 ; li r1,1 | lwz r1,0(r2) ; stw r1,0(r2) | lwsync ; sync | lwz r3,0(r2) ; lwz r3,0(r2) | xor r4,r3,r3 ; xor r4,r3,r3 | lwzx r5,r4,r6 ; lwzx r5,r4,r6 | ; lwsync | ; li r7,1 | ; stw r7,0(r6) | ; exists (0:r3=1 /\ 0:r5=0 /\ 1:r1=1 /\ 1:r3=1 /\ 1:r5=0)