Test W+WW+WR+wsiw0w0+rfih2w0+Ah0

X86_64 W+WW+WR+wsiw0w0+rfih2w0+Ah0
"WseAh0w0 Wsiw0w0 Wsew0h2 Rfih2w0 Frew0Ah0"
Cycle=Rfih2w0 Frew0Ah0 WseAh0w0 Wsiw0w0 Wsew0h2
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Ws Fr
Orig=WseAh0w0 Wsiw0w0 Wsew0h2 Rfih2w0 Frew0Ah0
{
1:rax=0x2020202; 1:rbx=0x3030303;
2:rax=x;
}
 P0            | P1            | P2                 ;
 movw $257,%ax | movl %eax,(x) | movw $1028,2(%rax) ;
 xchgw (x),%ax | movl %ebx,(x) | movl (x),%ebx      ;
Observed
    x=0x4040303; 2:rbx=0x4040202; 0:rax=0x202;