Test W+WW+WR+wsiw0w0+rfih0w0+Ah0

X86_64 W+WW+WR+wsiw0w0+rfih0w0+Ah0
"WseAh0w0 Wsiw0w0 Wsew0h0 Rfih0w0 Frew0Ah0"
Cycle=Rfih0w0 Frew0Ah0 WseAh0w0 Wsiw0w0 Wsew0h0
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Ws Fr
Orig=WseAh0w0 Wsiw0w0 Wsew0h0 Rfih0w0 Frew0Ah0
{
1:rax=0x2020202; 1:rbx=0x3030303;
}
 P0            | P1            | P2             ;
 movw $257,%ax | movl %eax,(x) | movw $1028,(x) ;
 xchgw (x),%ax | movl %ebx,(x) | movl (x),%eax  ;
Observed
    x=0x3030101; 2:rax=0x2020404; 0:rax=0x404;
and x=0x3030404; 2:rax=0x2020404; 0:rax=0x202;