Test W+WW+WR+wsih0h0+rfih2w0+Aw0

X86_64 W+WW+WR+wsih0h0+rfih2w0+Aw0
"WseAw0h0 Wsih0h0 Wseh0h2 Rfih2w0 Frew0Aw0"
Cycle=Wsih0h0 Wseh0h2 Rfih2w0 Frew0Aw0 WseAw0h0
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Ws Fr
Orig=WseAw0h0 Wsih0h0 Wseh0h2 Rfih2w0 Frew0Aw0
{
0:rax=0x1010101;
2:rax=x;
}
 P0             | P1            | P2                 ;
 movl %eax,%ebx | movw $514,(x) | movw $1028,2(%rax) ;
 xchgl (x),%ebx | movw $771,(x) | movl (x),%ebx      ;
Observed
    x=0x4040303; 2:rbx=0x4040202; 0:rbx=0x202;