Test W+WR+WW+rfih2w0+wsih0w0+Aw0

X86_64 W+WR+WW+rfih2w0+wsih0w0+Aw0
"WseAw0h2 Rfih2w0 Frew0h0 Wsih0w0 Wsew0Aw0"
Cycle=Wsih0w0 Wsew0Aw0 WseAw0h2 Rfih2w0 Frew0h0
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Ws
Orig=WseAw0h2 Rfih2w0 Frew0h0 Wsih0w0 Wsew0Aw0
{
0:rax=0x1010101;
1:rax=x;
2:rax=0x4040404;
}
 P0             | P1                | P2            ;
 movl %eax,%ebx | movw $514,2(%rax) | movw $771,(x) ;
 xchgl (x),%ebx | movl (x),%ebx     | movl %eax,(x) ;
Observed
    x=0x4040404; 1:rbx=0x2020303; 0:rbx=0x303;
and x=0x2020404; 1:rbx=0x2020303; 0:rbx=0x303;
and x=0x2020404; 1:rbx=0x2020101; 0:rbx=0x303;
and x=0x1010101; 1:rbx=0x2020303; 0:rbx=0x2020404;