Test W+WR+WW+rfih0w0+wsiw0w0+Aw0

X86_64 W+WR+WW+rfih0w0+wsiw0w0+Aw0
"WseAw0h0 Rfih0w0 Frew0w0 Wsiw0w0 Wsew0Aw0"
Cycle=Rfih0w0 Frew0w0 Wsiw0w0 Wsew0Aw0 WseAw0h0
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Ws
Orig=WseAw0h0 Rfih0w0 Frew0w0 Wsiw0w0 Wsew0Aw0
{
0:rax=0x1010101;
2:rax=0x3030303; 2:rbx=0x4040404;
}
 P0             | P1            | P2            ;
 movl %eax,%ebx | movw $514,(x) | movl %eax,(x) ;
 xchgl (x),%ebx | movl (x),%eax | movl %ebx,(x) ;
Observed
    x=0x1010202; 1:rax=0x3030202; 0:rbx=0x4040404;
and x=0x1010101; 1:rax=0x3030202; 0:rbx=0x4040202;
and x=0x4040404; 1:rax=0x3030202; 0:rbx=0x3030303;
and x=0x4040202; 1:rax=0x3030202; 0:rbx=0x3030303;