Test W+WR+WW+rfih0w0+wsih0h0+Aw0

X86_64 W+WR+WW+rfih0w0+wsih0h0+Aw0
"WseAw0h0 Rfih0w0 Frew0h0 Wsih0h0 Wseh0Aw0"
Cycle=Wsih0h0 Wseh0Aw0 WseAw0h0 Rfih0w0 Frew0h0
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Ws
Orig=WseAw0h0 Rfih0w0 Frew0h0 Wsih0h0 Wseh0Aw0
{
0:rax=0x1010101;
}
 P0             | P1            | P2             ;
 movl %eax,%ebx | movw $514,(x) | movw $771,(x)  ;
 xchgl (x),%ebx | movl (x),%eax | movw $1028,(x) ;
Observed
    x=0x1010202; 1:rax=0x202; 0:rbx=0x303;