Test W+WR+WR+rfiw0h2+rfih2w0+Aw0

X86_64 W+WR+WR+rfiw0h2+rfih2w0+Aw0
"WseAw0w0 Rfiw0h2 Freh2h2 Rfih2w0 Frew0Aw0"
Cycle=Freh2h2 Rfih2w0 Frew0Aw0 WseAw0w0 Rfiw0h2
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Fr
Orig=WseAw0w0 Rfiw0h2 Freh2h2 Rfih2w0 Frew0Aw0
{
0:rax=0x1010101;
1:rax=0x2020202; 1:rcx=x;
2:rax=x;
}
 P0             | P1               | P2                ;
 movl %eax,%ebx | movl %eax,(x)    | movw $771,2(%rax) ;
 xchgl (x),%ebx | movw 2(%rcx),%bx | movl (x),%ebx     ;
Observed
    x=0x3030101; 2:rbx=0x3030202; 1:rbx=0x303; 0:rbx=0x2020202;
and x=0x3030101; 2:rbx=0x3030202; 1:rbx=0x101; 0:rbx=0x2020202;
and x=0x3030101; 2:rbx=0x3030000; 1:rbx=0x101; 0:rbx=0x2020202;
and x=0x3030202; 2:rbx=0x3030101; 1:rbx=0x303; 0:rbx=0x0;