Test W+WR+WR+rfiw0h0+rfih0w0+Aw0

X86_64 W+WR+WR+rfiw0h0+rfih0w0+Aw0
"WseAw0w0 Rfiw0h0 Freh0h0 Rfih0w0 Frew0Aw0"
Cycle=Freh0h0 Rfih0w0 Frew0Aw0 WseAw0w0 Rfiw0h0
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Fr
Orig=WseAw0w0 Rfiw0h0 Freh0h0 Rfih0w0 Frew0Aw0
{
0:rax=0x1010101;
1:rax=0x2020202;
}
 P0             | P1            | P2            ;
 movl %eax,%ebx | movl %eax,(x) | movw $771,(x) ;
 xchgl (x),%ebx | movw (x),%bx  | movl (x),%eax ;
Observed
    x=0x1010303; 2:rax=0x303; 1:rbx=0x303; 0:rbx=0x2020202;
and x=0x1010303; 2:rax=0x2020303; 1:rbx=0x303; 0:rbx=0x2020202;
and x=0x1010303; 2:rax=0x303; 1:rbx=0x101; 0:rbx=0x2020202;
and x=0x1010303; 2:rax=0x2020303; 1:rbx=0x101; 0:rbx=0x2020202;
and x=0x2020303; 2:rax=0x1010303; 1:rbx=0x303; 0:rbx=0x0;