Test W+WR+WR+rfiw0h0+rfih0w0+Ah0

X86_64 W+WR+WR+rfiw0h0+rfih0w0+Ah0
"WseAh0w0 Rfiw0h0 Freh0h0 Rfih0w0 Frew0Ah0"
Cycle=Freh0h0 Rfih0w0 Frew0Ah0 WseAh0w0 Rfiw0h0
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Fr
Orig=WseAh0w0 Rfiw0h0 Freh0h0 Rfih0w0 Frew0Ah0
{
1:rax=0x2020202;
}
 P0            | P1            | P2            ;
 movw $257,%ax | movl %eax,(x) | movw $771,(x) ;
 xchgw (x),%ax | movw (x),%bx  | movl (x),%eax ;
Observed
    x=0x2020303; 2:rax=0x303; 1:rbx=0x303; 0:rax=0x202;