Test W+WR+WR+rfih2w0+rfiw0w0+Aw0

X86_64 W+WR+WR+rfih2w0+rfiw0w0+Aw0
"WseAw0h2 Rfih2w0 Frew0w0 Rfiw0w0 Frew0Aw0"
Cycle=Rfih2w0 Frew0w0 Rfiw0w0 Frew0Aw0 WseAw0h2
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Fr
Orig=WseAw0h2 Rfih2w0 Frew0w0 Rfiw0w0 Frew0Aw0
{
0:rax=0x1010101;
1:rax=x;
2:rax=0x3030303;
}
 P0             | P1                | P2            ;
 movl %eax,%ebx | movw $514,2(%rax) | movl %eax,(x) ;
 xchgl (x),%ebx | movl (x),%ebx     | movl (x),%ebx ;
Observed
    x=0x2020101; 2:rbx=0x2020101; 1:rbx=0x2020303; 0:rbx=0x3030303;
and x=0x2020101; 2:rbx=0x1010101; 1:rbx=0x2020303; 0:rbx=0x3030303;
and x=0x2020101; 2:rbx=0x2020101; 1:rbx=0x2020000; 0:rbx=0x3030303;