Test W+WR+WR+rfih2w0+rfih0w0+Aw0

X86_64 W+WR+WR+rfih2w0+rfih0w0+Aw0
"WseAw0h2 Rfih2w0 Frew0h0 Rfih0w0 Frew0Aw0"
Cycle=Rfih0w0 Frew0Aw0 WseAw0h2 Rfih2w0 Frew0h0
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Fr
Orig=WseAw0h2 Rfih2w0 Frew0h0 Rfih0w0 Frew0Aw0
{
0:rax=0x1010101;
1:rax=x;
}
 P0             | P1                | P2            ;
 movl %eax,%ebx | movw $514,2(%rax) | movw $771,(x) ;
 xchgl (x),%ebx | movl (x),%ebx     | movl (x),%eax ;
Observed
    x=0x2020101; 2:rax=0x1010101; 1:rbx=0x2020303; 0:rbx=0x303;
and x=0x1010303; 2:rax=0x2020303; 1:rbx=0x1010101; 0:rbx=0x2020000;
and x=0x2020303; 2:rax=0x303; 1:rbx=0x2020000; 0:rbx=0x0;