Test W+WR+WR+rfih2h2+rfih2w0+Aw0

X86_64 W+WR+WR+rfih2h2+rfih2w0+Aw0
"WseAw0h2 Rfih2h2 Freh2h2 Rfih2w0 Frew0Aw0"
Cycle=Rfih2h2 Freh2h2 Rfih2w0 Frew0Aw0 WseAw0h2
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Fr
Orig=WseAw0h2 Rfih2h2 Freh2h2 Rfih2w0 Frew0Aw0
{
0:rax=0x1010101;
1:rax=x;
2:rax=x;
}
 P0             | P1                | P2                ;
 movl %eax,%ebx | movw $514,2(%rax) | movw $771,2(%rax) ;
 xchgl (x),%ebx | movw 2(%rax),%bx  | movl (x),%ebx     ;
Observed
    x=0x3030101; 2:rbx=0x3030000; 1:rbx=0x101; 0:rbx=0x2020000;