Test W+WR+WR+rfih0w0+rfiw0h0+Aw0

X86_64 W+WR+WR+rfih0w0+rfiw0h0+Aw0
"WseAw0h0 Rfih0w0 Frew0w0 Rfiw0h0 Freh0Aw0"
Cycle=Rfih0w0 Frew0w0 Rfiw0h0 Freh0Aw0 WseAw0h0
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Fr
Orig=WseAw0h0 Rfih0w0 Frew0w0 Rfiw0h0 Freh0Aw0
{
0:rax=0x1010101;
2:rax=0x3030303;
}
 P0             | P1            | P2            ;
 movl %eax,%ebx | movw $514,(x) | movl %eax,(x) ;
 xchgl (x),%ebx | movl (x),%eax | movw (x),%bx  ;
Observed
    x=0x1010202; 2:rbx=0x202; 1:rax=0x3030202; 0:rbx=0x3030303;
and x=0x1010202; 2:rbx=0x101; 1:rax=0x3030202; 0:rbx=0x3030303;
and x=0x1010202; 2:rbx=0x101; 1:rax=0x202; 0:rbx=0x3030303;
and x=0x3030202; 2:rbx=0x202; 1:rax=0x1010202; 0:rbx=0x0;