Test W+WR+WR+rfih0w0+rfiw0h0+Ah0

X86_64 W+WR+WR+rfih0w0+rfiw0h0+Ah0
"WseAh0h0 Rfih0w0 Frew0w0 Rfiw0h0 Freh0Ah0"
Cycle=Rfih0w0 Frew0w0 Rfiw0h0 Freh0Ah0 WseAh0h0
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Fr
Orig=WseAh0h0 Rfih0w0 Frew0w0 Rfiw0h0 Freh0Ah0
{
2:rax=0x3030303;
}
 P0            | P1            | P2            ;
 movw $257,%ax | movw $514,(x) | movl %eax,(x) ;
 xchgw (x),%ax | movl (x),%eax | movw (x),%bx  ;
Observed
    x=0x3030202; 2:rbx=0x202; 1:rax=0x202; 0:rax=0x303;