Test W+WR+WR+rfih0h0+rfih2w0+Aw0

X86_64 W+WR+WR+rfih0h0+rfih2w0+Aw0
"WseAw0h0 Rfih0h0 Freh0h2 Rfih2w0 Frew0Aw0"
Cycle=Rfih0h0 Freh0h2 Rfih2w0 Frew0Aw0 WseAw0h0
Generator=diyone7 (version 7.54+05(dev))
Com=Ws Fr Fr
Orig=WseAw0h0 Rfih0h0 Freh0h2 Rfih2w0 Frew0Aw0
{
0:rax=0x1010101;
2:rax=x;
}
 P0             | P1            | P2                ;
 movl %eax,%ebx | movw $514,(x) | movw $771,2(%rax) ;
 xchgl (x),%ebx | movw (x),%ax  | movl (x),%ebx     ;
Observed
    x=0x3030101; 2:rbx=0x3030202; 1:rax=0x101; 0:rbx=0x202;
and x=0x3030101; 2:rbx=0x3030000; 1:rax=0x101; 0:rbx=0x202;