Test SB+posw0q0-poq0q0-posq0w0s004

AArch64 SB+posw0q0-poq0q0-posq0w0s004
"PosWWw0q0 PodWRq0q0 PosRRq0w0 Frew0w0 PosWWw0q0 PodWRq0q0 PosRRq0w0 Frew0w0"
Cycle=Frew0w0 PosWWw0q0 PodWRq0q0 PosRRq0w0 Frew0w0 PosWWw0q0 PodWRq0q0 PosRRq0w0
Relax=[PosWWw0q0,PodWRq0q0,PosRRq0w0]
Safe=Frew0w0
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=PosWWw0q0 PodWRq0q0 PosRRq0w0 Frew0w0 PosWWw0q0 PodWRq0q0 PosRRq0w0 Frew0w0
{
uint64_t y; uint64_t x; uint64_t 1:X5; uint64_t 1:X3; uint64_t 0:X5; uint64_t 0:X3;

0:X0=0x1010101; 0:X1=x; 0:X2=0x202020202020202; 0:X4=y;
1:X0=0x1010101; 1:X1=y; 1:X2=0x202020202020202; 1:X4=x;
}
 P0          | P1          ;
 STR W0,[X1] | STR W0,[X1] ;
 STR X2,[X1] | STR X2,[X1] ;
 LDR X3,[X4] | LDR X3,[X4] ;
 LDR W5,[X4] | LDR W5,[X4] ;
Observed
    y=0x202020202020202; x=0x202020202020202; 1:X5=0x0; 1:X3=0x202020202020202; 0:X5=0x2020202; 0:X3=0x202020202020202;
and y=0x202020202020202; x=0x202020202020202; 1:X5=0x0; 1:X3=0x0; 0:X5=0x0; 0:X3=0x202020202020202;
and y=0x202020202020202; x=0x202020202020202; 1:X5=0x0; 1:X3=0x202020202020202; 0:X5=0x0; 0:X3=0x0;