Test SB+poq0w0-posw0w0+poq0w0-posw0w4002

AArch64 SB+poq0w0-posw0w0+poq0w0-posw0w4002
"PodWRq0w0 PosRRw0w0 Frew0q0 PodWRq0w0 PosRRw0w4 Frew4q0"
Cycle=PosRRw0w0 Frew0q0 PodWRq0w0 PosRRw0w4 Frew4q0 PodWRq0w0
Relax=[PodWRq0w0,PosRRw0w0] [PodWRq0w0,PosRRw0w4]
Safe=Frew0q0 Frew4q0
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=PodWRq0w0 PosRRw0w0 Frew0q0 PodWRq0w0 PosRRw0w4 Frew4q0
{
uint64_t y; uint64_t x; uint64_t 1:X4; uint64_t 1:X2; uint64_t 0:X4; uint64_t 0:X2;

0:X0=0x101010101010101; 0:X1=x; 0:X3=y;
1:X0=0x101010101010101; 1:X1=y; 1:X3=x;
}
 P0          | P1             ;
 STR X0,[X1] | STR X0,[X1]    ;
 LDR W2,[X3] | LDR W2,[X3]    ;
 LDR W4,[X3] | LDR W4,[X3,#4] ;
Observed
    y=0x101010101010101; x=0x101010101010101; 1:X4=0x0; 1:X2=0x0; 0:X4=0x0; 0:X2=0x1010101;