Test S+posw0w0-pow0q0s001

AArch64 S+posw0w0-pow0q0s001
"PosWWw0w0 PodWWw0q0 Rfeq0w0 PosRRw0w0 PodRWw0q0 Wseq0w0"
Cycle=PosWWw0w0 PodWWw0q0 Rfeq0w0 PosRRw0w0 PodRWw0q0 Wseq0w0
Relax=[PosWWw0w0,PodWWw0q0] [PosRRw0w0,PodRWw0q0]
Safe=Rfeq0w0 Wseq0w0
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=PosWWw0w0 PodWWw0q0 Rfeq0w0 PosRRw0w0 PodRWw0q0 Wseq0w0
{
uint64_t y; uint64_t x; uint64_t 1:X5; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x2020202; 0:X1=x; 0:X2=0x3030303; 0:X3=0x101010101010101; 0:X4=y;
1:X1=y; 1:X3=0x101010101010101; 1:X4=x;
}
 P0          | P1          ;
 STR W0,[X1] | LDR W0,[X1] ;
 STR W2,[X1] | LDR W2,[X1] ;
 STR X3,[X4] | STR X3,[X4] ;
             | LDR X5,[X4] ;
Observed
    y=0x101010101010101; x=0x101010101010101; 1:X5=0x101010101010101; 1:X2=0x0; 1:X0=0x1010101;