Test S+posw0q0-poq0q0-posq0w4+posw4q0-poq0q0-posq0w4015

AArch64 S+posw0q0-poq0q0-posq0w4+posw4q0-poq0q0-posq0w4015
"PosWRw0q0 PodRRq0q0 PosRWq0w4 Rfew4w4 PosRRw4q0 PodRRq0q0 PosRWq0w4 Wsew4w0"
Cycle=PosWRw0q0 PodRRq0q0 PosRWq0w4 Rfew4w4 PosRRw4q0 PodRRq0q0 PosRWq0w4 Wsew4w0
Relax=[PosWRw0q0,PodRRq0q0,PosRWq0w4] [PosRRw4q0,PodRRq0q0,PosRWq0w4]
Safe=Wsew4w0 Rfew4w4
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=PosWRw0q0 PodRRq0q0 PosRWq0w4 Rfew4w4 PosRRw4q0 PodRRq0q0 PosRWq0w4 Wsew4w0
{
uint64_t y; uint64_t x; uint64_t 1:X6; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0; uint64_t 0:X3; uint64_t 0:X2;

0:X0=0x2020202; 0:X1=x; 0:X4=y; 0:X5=0x1010101;
1:X1=y; 1:X4=x; 1:X5=0x1010101;
}
 P0             | P1             ;
 STR W0,[X1]    | LDR W0,[X1,#4] ;
 LDR X2,[X1]    | LDR X2,[X1]    ;
 LDR X3,[X4]    | LDR X3,[X4]    ;
 STR W5,[X4,#4] | STR W5,[X4,#4] ;
                | LDR X6,[X4]    ;
Observed
    y=0x101010100000000; x=0x101010102020202; 1:X6=0x101010102020202; 1:X3=0x2020202; 1:X2=0x0; 1:X0=0x1010101; 0:X3=0x0; 0:X2=0x2020202;
and y=0x101010100000000; x=0x101010102020202; 1:X6=0x101010102020202; 1:X3=0x0; 1:X2=0x0; 1:X0=0x1010101; 0:X3=0x0; 0:X2=0x2020202;
and y=0x101010100000000; x=0x101010102020202; 1:X6=0x101010100000000; 1:X3=0x0; 1:X2=0x0; 1:X0=0x1010101; 0:X3=0x0; 0:X2=0x2020202;