Test RWC+posb0h0+rfib0h0+b1

AArch64 RWC+posb0h0+rfib0h0+b1
"Rfeb1b0 PosRRb0h0 Freh0b0 Rfib0h0 Freh0b1"
Cycle=Rfib0h0 Freh0b1 Rfeb1b0 PosRRb0h0 Freh0b0
Relax=Rfib0h0
Safe=PosRRb0h0 Rfeb1b0 Freh0b0 Freh0b1
Generator=diy7 (version 7.52+9(dev))
Prefetch=
Com=Rf Fr Fr
Orig=Rfeb1b0 PosRRb0h0 Freh0b0 Rfib0h0 Freh0b1
{
uint32_t x; uint32_t 2:X2; uint32_t 1:X2; uint32_t 1:X0;

0:X1=x;
1:X1=x;
2:X1=x;
}
 P0              | P1           | P2           ;
 MOV W0,#1       | LDRB W0,[X1] | MOV W0,#2    ;
 STRB W0,[X1,#1] | LDRH W2,[X1] | STRB W0,[X1] ;
                 |              | LDRH W2,[X1] ;
Observed
    x=0x102; 2:X2=0x102; 1:X2=0x100; 1:X0=0x2;
and x=0x102; 2:X2=0x2; 1:X2=0x0; 1:X0=0x2;
and x=0x102; 2:X2=0x102; 1:X2=0x0; 1:X0=0x2;