Test RWC+posb0b0+rfib0h0+h0

AArch64 RWC+posb0b0+rfib0h0+h0
"Rfeh0b0 PosRRb0b0 Freb0b0 Rfib0h0 Freh0h0"
Cycle=Freb0b0 Rfib0h0 Freh0h0 Rfeh0b0 PosRRb0b0
Relax=Rfib0h0
Safe=Freb0b0 PosRRb0b0 Rfeh0b0 Freh0h0
Generator=diy7 (version 7.52+9(dev))
Prefetch=
Com=Rf Fr Fr
Orig=Rfeh0b0 PosRRb0b0 Freb0b0 Rfib0h0 Freh0h0
{
uint32_t x; uint32_t 2:X2; uint32_t 1:X2; uint32_t 1:X0;

0:X1=x;
1:X1=x;
2:X1=x;
}
 P0           | P1           | P2           ;
 MOV W0,#257  | LDRB W0,[X1] | MOV W0,#2    ;
 STRH W0,[X1] | LDRB W2,[X1] | STRB W0,[X1] ;
              |              | LDRH W2,[X1] ;
Observed
    x=0x102; 2:X2=0x2; 1:X2=0x1; 1:X0=0x2;
and x=0x102; 2:X2=0x102; 1:X2=0x1; 1:X0=0x2;
and x=0x102; 2:X2=0x2; 1:X2=0x0; 1:X0=0x2;
and x=0x101; 2:X2=0x2; 1:X2=0x0; 1:X0=0x2;
and x=0x102; 2:X2=0x102; 1:X2=0x0; 1:X0=0x2;
and x=0x102; 2:X2=0x2; 1:X2=0x0; 1:X0=0x1;
and x=0x101; 2:X2=0x2; 1:X2=0x0; 1:X0=0x1;
and x=0x102; 2:X2=0x102; 1:X2=0x0; 1:X0=0x1;