Test R+posw4q0-poq0q0-posq0w4s011

AArch64 R+posw4q0-poq0q0-posq0w4s011
"PosWRw4q0 PodRRq0q0 PosRWq0w4 Wsew4w4 PosWWw4q0 PodWRq0q0 PosRRq0w4 Frew4w4"
Cycle=Frew4w4 PosWRw4q0 PodRRq0q0 PosRWq0w4 Wsew4w4 PosWWw4q0 PodWRq0q0 PosRRq0w4
Relax=[PosWWw4q0,PodWRq0q0,PosRRq0w4] [PosWRw4q0,PodRRq0q0,PosRWq0w4]
Safe=Frew4w4 Wsew4w4
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=PosWRw4q0 PodRRq0q0 PosRWq0w4 Wsew4w4 PosWWw4q0 PodWRq0q0 PosRRq0w4 Frew4w4
{
uint64_t y; uint64_t x; uint64_t 1:X5; uint64_t 1:X3; uint64_t 0:X6; uint64_t 0:X3; uint64_t 0:X2;

0:X0=0x1010101; 0:X1=x; 0:X4=y; 0:X5=0x1010101;
1:X0=0x2020202; 1:X1=y; 1:X2=0x303030303030303; 1:X4=x;
}
 P0             | P1             ;
 STR W0,[X1,#4] | STR W0,[X1,#4] ;
 LDR X2,[X1]    | STR X2,[X1]    ;
 LDR X3,[X4]    | LDR X3,[X4]    ;
 STR W5,[X4,#4] | LDR W5,[X4,#4] ;
 LDR X6,[X4]    |                ;
Observed
    y=0x303030303030303; x=0x101010100000000; 1:X5=0x0; 1:X3=0x101010100000000; 0:X6=0x101010100000000; 0:X3=0x0; 0:X2=0x101010100000000;
and y=0x101010103030303; x=0x101010100000000; 1:X5=0x0; 1:X3=0x101010100000000; 0:X6=0x101010100000000; 0:X3=0x0; 0:X2=0x101010100000000;