Test R+posw0q0-poq0q0-posq0w0+posw0q0-poq0q0-posq0w4007

AArch64 R+posw0q0-poq0q0-posq0w0+posw0q0-poq0q0-posq0w4007
"PosWWw0q0 PodWRq0q0 PosRWq0w0 Wsew0w0 PosWWw0q0 PodWRq0q0 PosRRq0w4 Frew4w0"
Cycle=Wsew0w0 PosWWw0q0 PodWRq0q0 PosRRq0w4 Frew4w0 PosWWw0q0 PodWRq0q0 PosRWq0w0
Relax=[PosWWw0q0,PodWRq0q0,PosRWq0w0] [PosWWw0q0,PodWRq0q0,PosRRq0w4]
Safe=Wsew0w0 Frew4w0
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=PosWWw0q0 PodWRq0q0 PosRWq0w0 Wsew0w0 PosWWw0q0 PodWRq0q0 PosRRq0w4 Frew4w0
{
uint64_t y; uint64_t x; uint64_t 1:X5; uint64_t 1:X3; uint64_t 0:X6; uint64_t 0:X3;

0:X0=0x1010101; 0:X1=x; 0:X2=0x202020202020202; 0:X4=y; 0:X5=0x1010101;
1:X0=0x2020202; 1:X1=y; 1:X2=0x303030303030303; 1:X4=x;
}
 P0          | P1             ;
 STR W0,[X1] | STR W0,[X1]    ;
 STR X2,[X1] | STR X2,[X1]    ;
 LDR X3,[X4] | LDR X3,[X4]    ;
 STR W5,[X4] | LDR W5,[X4,#4] ;
 LDR X6,[X4] |                ;
Observed
    y=0x303030301010101; x=0x202020202020202; 1:X5=0x0; 1:X3=0x202020202020202; 0:X6=0x303030301010101; 0:X3=0x303030303030303;
and y=0x303030301010101; x=0x202020202020202; 1:X5=0x0; 1:X3=0x202020202020202; 0:X6=0x303030301010101; 0:X3=0x0;
and y=0x303030303030303; x=0x202020202020202; 1:X5=0x0; 1:X3=0x202020202020202; 0:X6=0x1010101; 0:X3=0x0;
and y=0x303030301010101; x=0x202020202020202; 1:X5=0x0; 1:X3=0x202020202020202; 0:X6=0x1010101; 0:X3=0x0;