Test R+poq0w0-posw0w0+poq0w4-posw4w4003

AArch64 R+poq0w0-posw0w0+poq0w4-posw4w4003
"PodWRq0w0 PosRWw0w0 Wsew0q0 PodWRq0w4 PosRRw4w4 Frew4q0"
Cycle=PosRWw0w0 Wsew0q0 PodWRq0w4 PosRRw4w4 Frew4q0 PodWRq0w0
Relax=[PodWRq0w0,PosRWw0w0] [PodWRq0w4,PosRRw4w4]
Safe=Wsew0q0 Frew4q0
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=PodWRq0w0 PosRWw0w0 Wsew0q0 PodWRq0w4 PosRRw4w4 Frew4q0
{
uint64_t y; uint64_t x; uint64_t 1:X4; uint64_t 1:X2; uint64_t 0:X5; uint64_t 0:X2;

0:X0=0x101010101010101; 0:X1=x; 0:X3=y; 0:X4=0x1010101;
1:X0=0x202020202020202; 1:X1=y; 1:X3=x;
}
 P0          | P1             ;
 STR X0,[X1] | STR X0,[X1]    ;
 LDR W2,[X3] | LDR W2,[X3,#4] ;
 STR W4,[X3] | LDR W4,[X3,#4] ;
 LDR X5,[X3] |                ;
Observed
    y=0x202020202020202; x=0x101010101010101; 1:X4=0x0; 1:X2=0x1010101; 0:X5=0x1010101; 0:X2=0x0;
and y=0x202020201010101; x=0x101010101010101; 1:X4=0x0; 1:X2=0x1010101; 0:X5=0x1010101; 0:X2=0x0;