Test MP+posw4w4+posw4q0

AArch64 MP+posw4w4+posw4q0
"PosWWw4w4 Rfew4w4 PosRRw4q0 Freq0w4"
Cycle=Rfew4w4 PosRRw4q0 Freq0w4 PosWWw4w4
Relax=
Safe=Rfew4P PosWWw4P PosRRw4P Freq0P
Prefetch=
Com=Rf Fr
Orig=PosWWw4w4 Rfew4w4 PosRRw4q0 Freq0w4
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x1010101; 0:X1=x; 0:X2=0x2020202;
1:X1=x;
}
 P0             | P1             ;
 STR W0,[X1,#4] | LDR W0,[X1,#4] ;
 STR W2,[X1,#4] | LDR X2,[X1]    ;
                | LDR X3,[X1]    ;
Observed
    x=0x202020200000000; 1:X3=0x202020200000000; 1:X2=0x0; 1:X0=0x2020202;