Test MP+posw0w4+posq0w4

AArch64 MP+posw0w4+posq0w4
"PosWWw0w4 Rfew4q0 PosRRq0w4 Frew4w0"
Cycle=PosWWw0w4 Rfew4q0 PosRRq0w4 Frew4w0
Relax=
Safe=PosWWw0P Rfew4P Frew4P PosRRq0P
Prefetch=
Com=Rf Fr
Orig=PosWWw0w4 Rfew4q0 PosRRq0w4 Frew4w0
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x1010101; 0:X1=x; 0:X2=0x2020202;
1:X1=x;
}
 P0             | P1             ;
 STR W0,[X1]    | LDR X0,[X1]    ;
 STR W2,[X1,#4] | LDR W2,[X1,#4] ;
                | LDR X3,[X1]    ;
Observed
    x=0x202020201010101; 1:X3=0x202020201010101; 1:X2=0x0; 1:X0=0x202020201010101;