Test MP+posw0w0-pow0q0s003

AArch64 MP+posw0w0-pow0q0s003
"PosWRw0w0 PodRWw0q0 Rfeq0w0 PosRRw0w0 PodRRw0q0 Freq0w0"
Cycle=PosWRw0w0 PodRWw0q0 Rfeq0w0 PosRRw0w0 PodRRw0q0 Freq0w0
Relax=[PosWRw0w0,PodRWw0q0] [PosRRw0w0,PodRRw0q0]
Safe=Rfeq0w0 Freq0w0
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PosWRw0w0 PodRWw0q0 Rfeq0w0 PosRRw0w0 PodRRw0q0 Freq0w0
{
uint64_t y; uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0; uint64_t 0:X2;

0:X0=0x1010101; 0:X1=x; 0:X3=0x101010101010101; 0:X4=y;
1:X1=y; 1:X4=x;
}
 P0          | P1          ;
 STR W0,[X1] | LDR W0,[X1] ;
 LDR W2,[X1] | LDR W2,[X1] ;
 STR X3,[X4] | LDR X3,[X4] ;
Observed
    y=0x101010101010101; x=0x1010101; 1:X3=0x1010101; 1:X2=0x0; 1:X0=0x1010101; 0:X2=0x1010101;
and y=0x101010101010101; x=0x1010101; 1:X3=0x0; 1:X2=0x0; 1:X0=0x1010101; 0:X2=0x1010101;