Test MP+posq0w4+posq0w0

AArch64 MP+posq0w4+posq0w0
"PosWWq0w4 Rfew4q0 PosRRq0w0 Frew0q0"
Cycle=Frew0q0 PosWWq0w4 Rfew4q0 PosRRq0w0
Relax=
Safe=Frew0P Rfew4P PosWWq0P PosRRq0P
Prefetch=
Com=Rf Fr
Orig=PosWWq0w4 Rfew4q0 PosRRq0w0 Frew0q0
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x101010101010101; 0:X1=x; 0:X2=0x2020202;
1:X1=x;
}
 P0             | P1          ;
 STR X0,[X1]    | LDR X0,[X1] ;
 STR W2,[X1,#4] | LDR W2,[X1] ;
                | LDR X3,[X1] ;
Observed
    x=0x202020201010101; 1:X3=0x202020201010101; 1:X2=0x0; 1:X0=0x202020201010101;