Test MP+posq0w0+posq0w4

AArch64 MP+posq0w0+posq0w4
"PosWWq0w0 Rfew0q0 PosRRq0w4 Frew4q0"
Cycle=Rfew0q0 PosRRq0w4 Frew4q0 PosWWq0w0
Relax=
Safe=Rfew0P Frew4P PosWWq0P PosRRq0P
Prefetch=
Com=Rf Fr
Orig=PosWWq0w0 Rfew0q0 PosRRq0w4 Frew4q0
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x101010101010101; 0:X1=x; 0:X2=0x2020202;
1:X1=x;
}
 P0          | P1             ;
 STR X0,[X1] | LDR X0,[X1]    ;
 STR W2,[X1] | LDR W2,[X1,#4] ;
             | LDR X3,[X1]    ;
Observed
    x=0x101010102020202; 1:X3=0x101010102020202; 1:X2=0x0; 1:X0=0x101010102020202;