Test MP+poq0w4-posw4w0+poq0w4-posw4w4001

AArch64 MP+poq0w4-posw4w0+poq0w4-posw4w4001
"PodWWq0w4 PosWWw4w0 Rfew0q0 PodRRq0w4 PosRRw4w4 Frew4q0"
Cycle=Rfew0q0 PodRRq0w4 PosRRw4w4 Frew4q0 PodWWq0w4 PosWWw4w0
Relax=[PodWWq0w4,PosWWw4w0] [PodRRq0w4,PosRRw4w4]
Safe=Rfew0q0 Frew4q0
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWWq0w4 PosWWw4w0 Rfew0q0 PodRRq0w4 PosRRw4w4 Frew4q0
{
uint64_t y; uint64_t x; uint64_t 1:X4; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x101010101010101; 0:X1=x; 0:X2=0x1010101; 0:X3=y; 0:X4=0x2020202;
1:X1=y; 1:X3=x;
}
 P0             | P1             ;
 STR X0,[X1]    | LDR X0,[X1]    ;
 STR W2,[X3,#4] | LDR W2,[X3,#4] ;
 STR W4,[X3]    | LDR W4,[X3,#4] ;
Observed
    y=0x101010102020202; x=0x101010101010101; 1:X4=0x0; 1:X2=0x1010101; 1:X0=0x101010102020202;
and y=0x101010102020202; x=0x101010101010101; 1:X4=0x0; 1:X2=0x1010101; 1:X0=0x0;