Test MP+poq0w0-posw0w0s001

AArch64 MP+poq0w0-posw0w0s001
"PodWWq0w0 PosWWw0w0 Rfew0q0 PodRRq0w0 PosRRw0w0 Frew0q0"
Cycle=PosWWw0w0 Rfew0q0 PodRRq0w0 PosRRw0w0 Frew0q0 PodWWq0w0
Relax=[PodWWq0w0,PosWWw0w0] [PodRRq0w0,PosRRw0w0]
Safe=Rfew0q0 Frew0q0
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWWq0w0 PosWWw0w0 Rfew0q0 PodRRq0w0 PosRRw0w0 Frew0q0
{
uint64_t y; uint64_t x; uint64_t 1:X4; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x101010101010101; 0:X1=x; 0:X2=0x1010101; 0:X3=y; 0:X4=0x2020202;
1:X1=y; 1:X3=x;
}
 P0          | P1          ;
 STR X0,[X1] | LDR X0,[X1] ;
 STR W2,[X3] | LDR W2,[X3] ;
 STR W4,[X3] | LDR W4,[X3] ;
Observed
    y=0x2020202; x=0x101010101010101; 1:X4=0x0; 1:X2=0x1010101; 1:X0=0x2020202;
and y=0x2020202; x=0x101010101010101; 1:X4=0x0; 1:X2=0x1010101; 1:X0=0x0;