Test LB+posw0w0-pow0q0+posw4w4-pow4q0001

AArch64 LB+posw0w0-pow0q0+posw4w4-pow4q0001
"PosRWw0w0 PodWWw0q0 Rfeq0w4 PosRRw4w4 PodRWw4q0 Rfeq0w0"
Cycle=PosRWw0w0 PodWWw0q0 Rfeq0w4 PosRRw4w4 PodRWw4q0 Rfeq0w0
Relax=[PosRWw0w0,PodWWw0q0] [PosRRw4w4,PodRWw4q0]
Safe=Rfeq0w0 Rfeq0w4
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=PosRWw0w0 PodWWw0q0 Rfeq0w4 PosRRw4w4 PodRWw4q0 Rfeq0w0
{
uint64_t y; uint64_t x; uint64_t 1:X2; uint64_t 1:X0; uint64_t 0:X0;

0:X1=x; 0:X2=0x2020202; 0:X3=0x101010101010101; 0:X4=y;
1:X1=y; 1:X3=0x101010101010101; 1:X4=x;
}
 P0          | P1             ;
 LDR W0,[X1] | LDR W0,[X1,#4] ;
 STR W2,[X1] | LDR W2,[X1,#4] ;
 STR X3,[X4] | STR X3,[X4]    ;
Observed
    y=0x101010101010101; x=0x101010102020202; 1:X2=0x0; 1:X0=0x1010101; 0:X0=0x0;
and y=0x101010101010101; x=0x101010101010101; 1:X2=0x0; 1:X0=0x1010101; 0:X0=0x0;