Test CoRR+posw4w4+q0

AArch64 CoRR+posw4w4+q0
"Rfeq0w4 PosRRw4w4 Frew4q0"
Cycle=PosRRw4w4 Frew4q0 Rfeq0w4
Relax=
Safe=Frew4P PosRRw4P Rfeq0P
Prefetch=
Com=Rf Fr
Orig=Rfeq0w4 PosRRw4w4 Frew4q0
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x101010101010101; 0:X1=x;
1:X1=x;
}
 P0          | P1             ;
 STR X0,[X1] | LDR W0,[X1,#4] ;
             | LDR W2,[X1,#4] ;
             | LDR X3,[X1]    ;
Observed
    x=0x101010101010101; 1:X3=0x101010101010101; 1:X2=0x0; 1:X0=0x1010101;