Test CoRR+posw0w0+q0

AArch64 CoRR+posw0w0+q0
"Rfeq0w0 PosRRw0w0 Frew0q0"
Cycle=PosRRw0w0 Frew0q0 Rfeq0w0
Relax=
Safe=Frew0P PosRRw0P Rfeq0P
Prefetch=
Com=Rf Fr
Orig=Rfeq0w0 PosRRw0w0 Frew0q0
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x101010101010101; 0:X1=x;
1:X1=x;
}
 P0          | P1          ;
 STR X0,[X1] | LDR W0,[X1] ;
             | LDR W2,[X1] ;
             | LDR X3,[X1] ;
Observed
    x=0x101010101010101; 1:X3=0x101010101010101; 1:X2=0x0; 1:X0=0x1010101;