Test CoRR+posq0w4+w4

AArch64 CoRR+posq0w4+w4
"Rfew4q0 PosRRq0w4 Frew4w4"
Cycle=Frew4w4 Rfew4q0 PosRRq0w4
Relax=
Safe=Rfew4P Frew4P PosRRq0P
Prefetch=
Com=Rf Fr
Orig=Rfew4q0 PosRRq0w4 Frew4w4
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x1010101; 0:X1=x;
1:X1=x;
}
 P0             | P1             ;
 STR W0,[X1,#4] | LDR X0,[X1]    ;
                | LDR W2,[X1,#4] ;
                | LDR X3,[X1]    ;
Observed
    x=0x101010100000000; 1:X3=0x101010100000000; 1:X2=0x0; 1:X0=0x101010100000000;