Test CoRR+posq0q0+w0

AArch64 CoRR+posq0q0+w0
"Rfew0q0 PosRRq0q0 Freq0w0"
Cycle=Rfew0q0 PosRRq0q0 Freq0w0
Relax=
Safe=Rfew0P Freq0P PosRRq0P
Prefetch=
Com=Rf Fr
Orig=Rfew0q0 PosRRq0q0 Freq0w0
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x1010101; 0:X1=x;
1:X1=x;
}
 P0          | P1          ;
 STR W0,[X1] | LDR X0,[X1] ;
             | LDR X2,[X1] ;
             | LDR X3,[X1] ;
Observed
    x=0x1010101; 1:X3=0x1010101; 1:X2=0x0; 1:X0=0x1010101;