Test CoRR+frib0b0-rfib0h0-posh0b0+h0

AArch64 CoRR+frib0b0-rfib0h0-posh0b0+h0
"Rfeh0b0 Frib0b0 Rfib0h0 PosRRh0b0 Freb0h0"
Cycle=Frib0b0 Rfib0h0 PosRRh0b0 Freb0h0 Rfeh0b0
Relax=Rfib0h0
Safe=Frib0b0 Freb0h0 Rfeh0b0 PosRRh0b0
Generator=diy7 (version 7.52+9(dev))
Prefetch=
Com=Rf Fr
Orig=Rfeh0b0 Frib0b0 Rfib0h0 PosRRh0b0 Freb0h0
{
uint32_t x; uint32_t 1:X4; uint32_t 1:X3; uint32_t 1:X0;

0:X1=x;
1:X1=x;
}
 P0           | P1           ;
 MOV W0,#257  | LDRB W0,[X1] ;
 STRH W0,[X1] | MOV W2,#2    ;
              | STRB W2,[X1] ;
              | LDRH W3,[X1] ;
              | LDRB W4,[X1] ;
Observed
    x=0x101; 1:X4=0x2; 1:X3=0x101; 1:X0=0x0;