Test S+dmb.syw0w4+pospw0-ctrlisbw0w4-friw4p

AArch64 S+dmb.syw0w4+pospw0-ctrlisbw0w4-friw4p
"DMB.SYdWWw0w4 Rfew4P PosRRPw0 DpCtrlIsbdRw0w4 Friw4P WsePw0"
Cycle=WsePw0 DMB.SYdWWw0w4 Rfew4P PosRRPw0 DpCtrlIsbdRw0w4 Friw4P
Relax=Fri PosRR
Safe=[Wse,w0,DMB.SYdWW,w4,Rfe] DpCtrlIsbdR w0 w4
Generator=diy7 (version 7.50+1(dev))
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMB.SYdWWw0w4 Rfew4P PosRRPw0 DpCtrlIsbdRw0w4 Friw4P WsePw0
{
uint64_t y; uint64_t x; uint64_t 1:X3; uint64_t 1:X0;

0:X0=0x2020202; 0:X1=x; 0:X2=0x1010101; 0:X3=y;
1:X1=y; 1:X4=x;
}
 P0             | P1             ;
 STR W0,[X1]    | LDR X0,[X1]    ;
 DMB SY         | LDR W2,[X1]    ;
 STR W2,[X3,#4] | CBNZ X2,LC00   ;
                | LC00:          ;
                | ISB            ;
                | LDR W3,[X4,#4] ;
                | MOV X5,#1      ;
                | STR X5,[X4]    ;
Observed
    y=0x101010100000000; x=0x2020202; 1:X3=0x0; 1:X0=0x101010100000000;