AArch64 MP+dmb.syw0w4+pospw0-ctrlw0q0-rfiq0p
"DMB.SYdWWw0w4 Rfew4P PosRRPw0 DpCtrldWw0q0 Rfiq0P FrePw0"
Cycle=FrePw0 DMB.SYdWWw0w4 Rfew4P PosRRPw0 DpCtrldWw0q0 Rfiq0P
Relax=Rfi PosRR
Safe=[Fre,w0,DMB.SYdWW,w4,Rfe] DpCtrldW w0 q0
Generator=diy7 (version 7.50+1(dev))
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMB.SYdWWw0w4 Rfew4P PosRRPw0 DpCtrldWw0q0 Rfiq0P FrePw0
{
uint64_t y; uint64_t x; uint64_t 1:X5; uint64_t 1:X0;
0:X0=0x2020202; 0:X1=x; 0:X2=0x1010101; 0:X3=y;
1:X1=y; 1:X3=0x101010101010101; 1:X4=x;
}
P0 | P1 ;
STR W0,[X1] | LDR X0,[X1] ;
DMB SY | LDR W2,[X1] ;
STR W2,[X3,#4] | CBNZ X2,LC00 ;
| LC00: ;
| STR X3,[X4] ;
| LDR X5,[X4] ;
Observed
y=0x101010100000000; x=0x101010102020202; 1:X5=0x101010102020202; 1:X0=0x101010100000000;
and y=0x101010100000000; x=0x101010102020202; 1:X5=0x101010101010101; 1:X0=0x101010100000000;